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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit mc-242452 mcp (multi-chip package) flash memory and mobile specified ram 32m-bit flash memory and 16m-bit cmos mobile specified ram data sheet document no. m15414ej3v0ds00 (3rd edition) date published march 2002 ns cp (k) printed in japan the mark shows major revised points. description the mc-242452 is a stacked type mcp (multi-chip package) of 33,554,432 bits (byte mode : 4,194,304 words by 8 bits, word mode : 2,097,152 words by 16 bits) flash memory and 16,777,216 bits (1,048,576 words by 16 bits) mobile specified ram. the mc-242452 is packaged in a 77-pin tape fbga and 71-pin tape fbga. features general features ? fast access time : t acc = 90 ns (max.), 85 ns (max.) (v cc f 2.7 v) (flash memory) t aa = 80, 90, 100 ns (max.) (mobile specified ram) ? supply voltage : v cc f / v cc m = 2.6 to 3.0 v ? wide operating temperature : t a = ? 20 to +70 c flash memory features ? two bank organization enabling simultaneous execution of program / erase and read ? bank organization : 2 banks (4m bits + 28m bits) ? memory organization : 4,194,304 words 8 bits (byte mode) 2,097,152 words 16 bits (word mode) ? sector organization : 71 sectors (8k bytes / 4k words 8 sectors, 64k bytes / 32k words 63 sectors) ? boot sector allocated to the lowest address (sector) ? 3-state output ? automatic program ? program suspend / resume ? unlock bypass program ? automatic erase ? chip erase ? sector erase (sectors can be combined freely) ? erase suspend / resume ? program / erase completion detection ? detection through data polling and toggle bits ? detection through ry (/by) pin ? sector group protection ? any sector can be protected ? any protected sector can be temporary unprotected ? sectors can be used for boot application ? hardware reset and standby using /reset pin ? automatic sleep mode ? boot block sector protect by /wp (acc) pin ? conforms to common flash memory interface (cfi) ? extra one time protect sector provided mobile specified ram features ? memory organization : 1,048,576 words by 16 bits ? supply current : at operating : 35 ma (max.) at standby mode 1 : 100 a (max.) at standby mode 2 : 10 a (max.) ? chip enable inputs : /cem ? byte data control : /lb, /ub ? standby mode input : mode ? standby mode 1 : normal standby (memory cell data hold valid) ? standby mode 2 : memory cell data hold invalid !
data sheet m15414ej3v0ds 2 mc-242452 ordering information part number flash memory flash memory mobile specified ram package boot sector access time access time ns (max.) ns (max.) mc-242452f9-b90-bt3 bottom address (sector) 90 80 77-pin tape fbga mc-242452f9-b95-bt3 note (b type) 85 (v cc f 2.7 v) 90 (12 7) MC-242452F9-B10-BT3 100 mc-242452f9-b90-bs1 note 80 71-pin tape fbga mc-242452f9-b95-bs1 note 90 (11 7) mc-242452f9-b10-bs1 note 100 note under development ! ! !
data sheet m15414ej3v0ds 3 mc-242452 pin configurations /xxx indicates active low si gnal. 77-pin tape fbga (12 7) v ss i/o9 i/o5 a7 /oe i/o7 i/o4 i/o0 a6 a18 a11 a8 a5 i/o8 i/o12 a13 a17 nc /cef i/o10 v cc f /we v cc m a16 i/o11 ry(/by) /reset a12 i/o6 i/o13 a9 a15 a19 i/o14 /cem i/o15, a-1 i/o1 a1 a2 a4 a10 nc i/o2 a0 a3 mode a20 a14 /lb ciof /wp(acc) /ub i/o3 ic ic v ss a bcdefghj klm n p nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc top view 8 7 6 5 4 3 2 1 71-pin tape fbga (11 7) top view vss i/o9 i/o5 a7 /oe i/o7 i/o4 i/o0 a6 a18 a11 a8 a5 i/o8 i/o12 a13 a17 nc /cef i/o10 v cc f /we v cc m a16 i/o11 ry(/by) /reset a12 i/o6 i/o13 a9 a15 a19 i/o14 /cem i/o15, a-1 i/o1 a1 a2 a4 a10 nc i/o2 a0 a3 mode a20 a14 /lb ciof /wp(acc) /ub i/o3 nc ic vss 8 7 6 5 4 3 2 1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc a bcdefghj klm common pins a0 - a19 : address inputs i/o0 - i/o15 : data inputs / outputs /oe : output enable /we : write enable v ss : ground nc note 1 : no connection ic note 2 : internal connection flash memory pins a20 : address inputs i/o15, a ? 1 : data inputs / outputs 15 (word mode) lsb address input (byte mode) /cef : chip enable ry (/by) : ready (busy) output /reset : hardware reset input v cc f : supply voltage /wp(acc) : hardware write protect (acceleration) ciof : selects 8-bit or 16-bit mode mobile specified ram pins /cem : chip enable mode : standby mode select v cc m : supply voltage /lb, /ub : byte data select note 1. some signals can be applied because this pin is not internally connected. 2. leave this pin connected to v ss or unconnected (recommended to connected to v ss ). remark refer to package drawings for the index mark. !
data sheet m15414ej3v0ds 4 mc-242452 block diagram 32 m-bit flash memory 4,194,304 words by 8 bits 2,097,152 words by 16 bits /we /oe /cem /reset /cef i/o0 - i/o15, a-1 a0 - a20 16 m-bit mobile specified ram (1,048,576 words by 16 bits) ry (/by) a0 - a19 a0 - a20 v cc f v ss v cc m v ss mode /lb /ub ciof /wp(acc)
data sheet m15414ej3v0ds 5 mc-242452 bus operations table operation flash memory mobile specified ram common /reset /cef ciof /wp(acc) /cem mode /lb /ub /oe /we i/o0 - i/o7 i/o8-i/o15 full standby standby mode 1 h h hh hi-z hi-z standby mode 2 h l output disable h l lh h h hi-z hi-z read (flash byte mode h l l note 2 l h data out hi-z memory note 1 ) word mode h data out data out write (flash byte mode h l l note 2 h l data in hi-z memory) word mode h data in data in temporary sector group v id note 2 hi-z or hi-z or unprotect data in/out data in/out boot block sector protect l hi-z or data in/out hi-z or data in/out flash memory hardware reset l hi-z hi-z read note 3 l h l l l h data out data out (mobile specified ram) h hi-z h l hi-z data out write note 3 lhll l data in data in (mobile specified ram) h hi-z h l hi-z data in caution other operations except for indicated in this table are inhibited. notes 1. when /oe = v il , v il can be applied to /we. when /oe = v ih , a write operation is started. 2. mobile specified ram should be standby. 3. flash memory should be standby or hardware reset. remarks 1. : v ih or v il , h : v ih , l : v il 2. sector group protection and read the product id are using a command. 3. mode pin of mobile specified ram must be fixed to h during active operation. 4. refer to dual operation flash memory 32m bits a series information (m14914e) for bus operations of flash memory. !
data sheet m15414ej3v0ds 6 mc-242452 sector organization / sector address table (flash memory) flash memory bottom boot (1/2) bank sector address sectors sector address table organization address bank address table k bytes / k words byte mode word mode a20 a19 a18 a17 a16 a15 a14 a13 a12 bank 2 64/32 3fffffh 1fffffh fsa70 1 1 1 1 1 1 x x x 3f0000h 1f8000h 64/32 3effffh 1f7fffh fsa69 111110xxx 3e0000h 1f0000h 64/32 3dffffh 1effffh fsa68 111101xxx 3d0000h 1e8000h 64/32 3cffffh 1e7fffh fsa67 111100xxx 3c0000h 1e0000h 64/32 3bffffh 1dffffh fsa66 111011xxx 3b0000h 1d8000h 64/32 3affffh 1d7fffh fsa65 111010xxx 3a0000h 1d0000h 64/32 39ffffh 1cffffh fsa64 111001xxx 390000h 1c8000h 64/32 38ffffh 1c7fffh fsa63 111000xxx 380000h 1c0000h 64/32 37ffffh 1bffffh fsa62 110111xxx 370000h 1b8000h 64/32 36ffffh 1b7fffh fsa61 110110xxx 360000h 1b0000h 64/32 35ffffh 1affffh fsa60 110101xxx 350000h 1a8000h 64/32 34ffffh 1a7fffh fsa59 110100xxx 340000h 1a0000h 64/32 33ffffh 19ffffh fsa58 110011xxx 330000h 198000h 64/32 32ffffh 197fffh fsa57 110010xxx 320000h 190000h 64/32 31ffffh 18ffffh fsa56 110001xxx 310000h 188000h 64/32 30ffffh 187fffh fsa55 110000xxx 300000h 180000h 64/32 2fffffh 17ffffh fsa54 101111xxx 2f0000h 178000h 64/32 2effffh 177fffh fsa53 101110xxx 2e0000h 170000h 64/32 2dffffh 16ffffh fsa52 101101xxx 2d0000h 168000h 64/32 2cffffh 167fffh fsa51 101100xxx 2c0000h 160000h 64/32 2bffffh 15ffffh fsa50 101011xxx 2b0000h 158000h 64/32 2affffh 157fffh fsa49 101010xxx 2a0000h 150000h 64/32 29ffffh 14ffffh fsa48 101001xxx 290000h 148000h 64/32 28ffffh 147fffh fsa47 101000xxx 280000h 140000h 64/32 27ffffh 13ffffh fsa46 100111xxx 270000h 138000h 64/32 26ffffh 137fffh fsa45 100110xxx 260000h 130000h 64/32 25ffffh 12ffffh fsa44 100101xxx 250000h 128000h 64/32 24ffffh 127fffh fsa43 100100xxx 240000h 120000h 64/32 23ffffh 11ffffh fsa42 100011xxx 230000h 118000h 64/32 22ffffh 117fffh fsa41 100010xxx 220000h 110000h 64/32 21ffffh 10ffffh fsa40 100001xxx 210000h 108000h 64/32 20ffffh 107fffh fsa39 100000xxx 200000h 100000h 64/32 1fffffh 0fffffh fsa38 011111xxx 1f0000h 0f8000h 64/32 1effffh 0f7fffh fsa37 011110xxx 1e0000h 0f0000h 64/32 1dffffh 0effffh fsa36 011101xxx 1d0000h 0e8000h 64/32 1cffffh 0e7fffh fsa35 011100xxx 1c0000h 0e0000h
data sheet m15414ej3v0ds 7 mc-242452 (2/2) bank sector address sectors sector address table organization address bank address table k bytes / k words byte mode word mode a20 a19 a18 a17 a16 a15 a14 a13 a12 bank 2 64/32 1bffffh 0dffffh fsa34 011011xxx 1b0000h 0d8000h 64/32 1affffh 0d7fffh fsa33 011010xxx 1a0000h 0d0000h 64/32 19ffffh 0cffffh fsa32 011001xxx 190000h 0c8000h 64/32 18ffffh 0c7fffh fsa31 011000xxx 180000h 0c0000h 64/32 17ffffh 0bffffh fsa30 010111xxx 170000h 0b8000h 64/32 16ffffh 0b7fffh fsa29 010110xxx 160000h 0b0000h 64/32 15ffffh 0affffh fsa28 010101xxx 150000h 0a8000h 64/32 14ffffh 0a7fffh fsa27 010100xxx 140000h 0a0000h 64/32 13ffffh 09ffffh fsa26 010011xxx 130000h 098000h 64/32 12ffffh 097fffh fsa25 010010xxx 120000h 090000h 64/32 11ffffh 08ffffh fsa24 010001xxx 110000h 088000h 64/32 10ffffh 087fffh fsa23 010000xxx 100000h 080000h 64/32 0fffffh 07ffffh fsa22 001111xxx 0f0000h 078000h 64/32 0effffh 077fffh fsa21 001110xxx 0e0000h 070000h 64/32 0dffffh 06ffffh fsa20 001101xxx 0d0000h 068000h 64/32 0cffffh 067fffh fsa19 001100xxx 0c0000h 060000h 64/32 0bffffh 05ffffh fsa18 001011xxx 0b0000h 058000h 64/32 0affffh 057fffh fsa17 001010xxx 0a0000h 050000h 64/32 09ffffh 04ffffh fsa16 001001xxx 090000h 048000h 64/32 08ffffh 047fffh fsa15 001000xxx 080000h 040000h bank 1 64/32 07ffffh 03ffffh fsa14 000111xxx 070000h 038000h 64/32 06ffffh 037fffh fsa13 000110xxx 060000h 030000h 64/32 05ffffh 02ffffh fsa12 000101xxx 050000h 028000h 64/32 04ffffh 027fffh fsa11 000100xxx 040000h 020000h 64/32 03ffffh 01ffffh fsa10 000011xxx 030000h 018000h 64/32 02ffffh 017fffh fsa9 000010xxx 020000h 010000h 64/32 01ffffh 00ffffh fsa8 000001xxx 010000h 008000h 8/4 00ffffh 007fffh fsa7 000000111 00e000h 007000h 8/4 00dfffh 006fffh fsa6 000000110 00c000h 006000h 8/4 00bfffh 005fffh fsa5 000000101 00a000h 005000h 8/4 009fffh 004fffh fsa4 000000100 008000h 004000h 8/4 007fffh 003fffh fsa3 000000011 006000h 003000h 8/4 005fffh 002fffh fsa2 000000010 004000h 002000h 8/4 003fffh 001fffh fsa1 000000001 002000h 001000h 8/4 001fffh 000fffh fsa0 000000000 000000h 000000h
data sheet m15414ej3v0ds 8 mc-242452 sector group address table (flash memory) sector group a20 a19 a18 a17 a16 a15 a14 a13 a12 size sector sga0 0000000008k bytes (1 sector) fsa0 sga1 0000000018k bytes (1 sector) fsa1 sga2 0000000108k bytes (1 sector) fsa2 sga3 0000000118k bytes (1 sector) fsa3 sga4 0000001008k bytes (1 sector) fsa4 sga5 0000001018k bytes (1 sector) fsa5 sga6 0000001108k bytes (1 sector) fsa6 sga7 0000001118k bytes (1 sector) fsa7 sga8 000001 192k bytes (3 sectors) fsa8?fsa10 10 11 sga9 0 0 0 1 256k bytes (4 sectors) fsa11?fsa14 sga10 0 0 1 0 256k bytes (4 sectors) fsa15?fsa18 sga11 0 0 1 1 256k bytes (4 sectors) fsa19?fsa22 sga12 0 1 0 0 256k bytes (4 sectors) fsa23?fsa26 sga13 0 1 0 1 256k bytes (4 sectors) fsa27?fsa30 sga14 0 1 1 0 256k bytes (4 sectors) fsa31?fsa34 sga15 0 1 1 1 256k bytes (4 sectors) fsa35?fsa38 sga16 1 0 0 0 256k bytes (4 sectors) fsa39?fsa42 sga17 1 0 0 1 256k bytes (4 sectors) fsa43?fsa46 sga18 1 0 1 0 256k bytes (4 sectors) fsa47?fsa50 sga19 1 0 1 1 256k bytes (4 sectors) fsa51?fsa54 sga20 1 1 0 0 256k bytes (4 sectors) fsa55?fsa58 sga21 1 1 0 1 256k bytes (4 sectors) fsa59?fsa62 sga22 1 1 1 0 256k bytes (4 sectors) fsa63?fsa66 sga23 111100 192k bytes (3 sectors) fsa67?fsa69 01 10 sga24 111111 64k bytes (1 sector) fsa70 remark : v ih or v il !
data sheet m15414ej3v0ds 9 mc-242452 command sequence (flash memory) command sequence bus 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle cycle address data address data address data address data address data address data read / reset note1 1 hf0hrard???????? read / reset note1 byte mode 3 aaah aah 555h 55h aaah f0h ra rd ? ? ? ? word mode 555h 2aah 555h program byte mode 4 aaah aah 555h 55h aaah a0h pa pd ? ? ? ? word mode 555h 2aah 555h program suspend note 2 1bab0h?????????? program resume note 3 1ba30h?????????? chip erase byte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h aaah 10h word mode 555h 2aah 555h 555h 2aah 555h sector erase byte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h fsa 30h word mode 555h 2aah 555h 555h 2aah sector erase suspend note 4 1bab0h?????????? sector erase resume note 5 1ba30h?????????? unlock bypass set byte mode 3 aaah aah 555h 55h aaah 20h ?????? word mode 555h 2aah 555h unlock bypass program note 6 2 ha0hpapd???????? unlock bypass reset note 6 2 ba 90h h 00h note11 ???????? product id byte mode 3 aaah aah 555h 55h (ba) 90h ia id ? ? ? ? aaah word mode 555h 2aah (ba) 555h sector group protection note 7 4 h 60h spa 60h spa 40h spa sd ? ? ? ? sector group unprotect note 8 4 h 60h sua 60h sua 40h sua sd ? ? ? ? query note 9 byte mode1aah98h?????????? word mode 55h extra one time protect byte mode 3 aaah aah 555h 55h aaah 88h ?????? sector entry word mode 555h 2aah 555h extra one time protect byte mode 4 aaah aah 555h 55h aaah a0h pa pd ? ? ? ? sector program note 10 word mode 555h 2aah 555h extra one time protect byte mode 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h eotpsa 30h sector erase note 10 word mode 555h 2aah 555h 555h 2aah extra one time protect byte mode 4 aaah aah 555h 55h aaah 90h xxxh 00h ? ? ? ? sector reset note 10 word mode 555h 2aah 555h extra one time protect sector 4 h 60h eotpsa 60h eotpsa 40h eotpsa sd ? ? ? ? protection note 10
data sheet m15414ej3v0ds 10 mc-242452 notes 1. both these read / reset commands reset the device to the read mode. 2. programming is suspended if b0h is input to the bank address being programmed to in a program operation. 3. programming is resumed if 30h is input to the bank address being suspended to in a program-suspend operation. 4. erasure is suspended if b0h is input to the bank address being erased in a sector erase operation. 5. erasure is resumed if 30h is input to the bank address being suspended in a sector-erase-suspend operation. 6. valid only in the unlock bypass mode. 7. valid only when /reset = v id (except in the extra one time protect sector mode). 8. the command sequence that protects a sector group is excluded. 9. only a0 to a6 are valid as an address. 10. valid only in the extra one time protect sector mode. 11. this command can be used even if this data is f0h. remarks 1. specify address 555h (a10 to a0) in the word mode, and aaah (a10 to a0, a-1) in the byte mode. 2. ra : read address rd : read data ia : address input xx00h (to read the manufacturer code) xx02h (to read the device code in the byte mode) xx01h (to read the device code in the word mode) id : code output. refer to the product id code (manufacturer code / device code) (flash memory) . pa : program address pd : program data fsa: erase sector address. the sector to be erased is selected by the combination of this address. refer to the sector organization / sector address table (flash memory) . ba : bank address. refer to the sector organization / sector address table (flash memory) . spa : sector group address to be protected. set sector group address (sga) and (a6, a1, a0) = (v il , v ih , v il ). for the sector group address, refer to the sector group address table (flash memory) . sua : unprotect sector group address. set sector group address (sga) and (a6, a1, a0) = (v ih , v ih , v il ). for the sector group address, refer to the sector group address table (flash memory) . sd : data for verifying whether sector groups read from the address specified by spa, sua, and eotpsa are protected. eotpsa : extra one time protect sector area addresses. byte mode : 000000h to 00ffffh, word mode : 000000h to 007fffh 3. the sector group address is don't care except when a program / erase address or read address are selected. 4. for the operation of the bus, refer to bus operations table . 5. of address bit indicates v ih or v il . 6. refer to dual operation flash memory 32m bits a series information (m14914e) for commands of flash memory. ! ! !
data sheet m15414ej3v0ds 11 mc-242452 product id code (manufacturer code / device code) (flash memory) product id code address inputs output a6 a1 a0 hex manufacturer code l l l 10h device code l l h 56h (byte mode), 2256h (word mode) product id code code outputs i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 hex manufacturer code 0000000000010000 10h device codebyte modea-1xxxxxxx010 10110 56h word mode0010001001010110 2256h remark h : v ih , l : v il , x : hi-z hardware sequence flags, hardware data protection (flash memory) refer to dual operation flash memory 32m bits a series information (m14914e). !
data sheet m15414ej3v0ds 12 mc-242452 initialization (mobile specified ram) the mc-242452 is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, before turning on the power, a 200 s or longer wait time must precede any signal toggling. (2) after the wait time, read operation must be performed at least 8 times. after that, it can be normal operation. figure 1. initialization timing chart address (input) /cem (input) v cc m v cc m (min.) v ih (min.) v ih (min.) mode (input) t rc t cp wait time power on read operation 8 times normal operation 200 s cautions 1. following power application, make mode and /cem high level during the wait time interval. 2. following power application, make mode high level during the wait time and eight read operations. 3. the read operation must satisfy the specs (read cycle (mobile specified ram)). 4. the address is don?t care (v ih or v il ) during read operation. 5. read operation must be executed with toggled the /cem pin. 6. to prevent bus contention, it is recommended to set /oe to high level. however, do not input data to the i/o pins if /oe is low level during a read operation.
data sheet m15414ej3v0ds 13 mc-242452 standby mode (flash memory) standby mode 1 and standby mode 2 differ as shown below. table 1. standby mode characteristics standby mode memory cell data hold standby supply current ( a) mode 1 valid 100 (i sb1 ) mode 2 invalid 10 (i sb2 ) standby mode state machine (flash memory) (1) from active to shift from this state to standby mode 1, change /cem from v il to v ih . to shift from this state to standby mode 2, change /cem from v il to v ih and change mode from v ih to v il . (2) from standby mode 1 to shift from this state to active, change /cem from v ih to v il . to shift from this state to standby mode 2, change mode from v ih to v il . (3) from standby mode 2 when shifting from this state to the active state or to standby mode 1, it is necessary to set mode to v ih and perform a dummy read operation 8 times after waiting for 200 s, in the same way as at power application. refer to figure 33. standby mode 2 entry and recovery timing chart (mobile specified ram) . after shifting to active state, change /cem to v il . after shifting to standby mode 1, do not change either mode or /cem. figure 2. standby mode state machine /cem = v ih , mode = v ih mode = v ih /cem = v ih , mode = v ih /cem = v ih , mode = v il /cem = v ih , mode = v il /cem = v il , mode = v ih /cem = v ih , mode = v ih /cem = v il wait 200 s, dummy read (8 times) power on initial state active standby mode 1 standby mode 2
data sheet m15414ej3v0ds 14 mc-242452 electrical specifications before turning on power, input v ss 0.2 v to the /reset pin until v cc f v cc f (min.). absolute maximum ratings parameter symbol condition rating unit supply voltage v cc f with respect to v ss ? 0.5 to +4.0 v v cc m with respect to v ss ? 0.5 to +4.0 input / output voltage v t with respect /wp(acc), /reset ? 0.5 note 1 to +13.0 v to v ss except /wp(acc), /reset ? 0.5 note 1 to v cc f, v cc m + 0.4 (4.0 v max.) note 2 ambient operation temperature t a ? 20 to +70 c storage temperature t stg ? 55 to +125 c notes 1. ? 1.0 v (min.) (pulse width 20 ns) 2. v cc f, v cc m + 0.5 v (max.) (pulse width 20 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions common parameter symbol condition min. typ. max. unit supply voltage v cc f, v cc m2.63.0v ambient operation temperature t a ? 20 +70 c flash memory parameter symbol condition min. typ. max. unit high level input voltage v ih 2.4 v cc f + 0.3 v low level input voltage v il ? 0.3 +0.5 v mobile specified ram parameter symbol condition min. typ. max. unit high level input voltage v ih v cc m x 0.8 v cc m + 0.3 v low level input voltage v il ? 0.3 note v cc m x 0.2 v note ? 0.5 v (min.) (pulse width: 30 ns)
data sheet m15414ej3v0ds 15 mc-242452 dc characteristics (recommended operating conditions unless otherwise noted) common parameter symbol test condition min. typ. max. unit input leakage current i li ? 1.0 +1.0 a output leakage current i lo ? 1.0 +1.0 a flash memory parameter symbol test condition min. typ. max. unit high level output voltage v oh i oh = ? 500 a, v cc f = v cc f (min.) v cc f ? 0.3 v low level output voltage v ol i ol = +1.0 ma, v cc f = v cc f (min.) 0.3 v power read byte mode i cc1 fv cc f = v cc f (max.), t cycle = 5 mhz 10 16 ma supply /cef = v il , /oe = v ih t cycle = 1 mhz 2 4 current word mode t cycle = 5 mhz 10 16 t cycle = 1 mhz 2 4 program, erase i cc2 fv cc f = v cc f (max.), /cef = v il , /oe = v ih 15 30 ma standby i cc3 fv cc f = v cc f (max.), /cef = /reset = 0.2 5 a /wp(acc) = v cc f 0.3 v, /oe = v il standby / reset i cc4 fv cc f = v cc f (max.), /reset = v ss 0.2 v 0.2 5 a automatic sleep mode i cc5 fv ih = v cc f 0.2 v, v il = v ss 0.2 v 0.2 5 a read during programming i cc6 fv ih = v cc f 0.2 v, v il = v ss 0.2 v 21 45 ma read during erasing i cc7 fv ih = v cc f 0.2 v, v il = v ss 0.2 v 21 45 ma programming i cc8 f/cef = v il , /oe = v ih ,1735ma during suspend automatic programming during suspend accelerated i acc /wp (acc) pin 5 10 ma programming v cc f1530 /reset high level input voltage v id high voltage is applied 11.5 12.5 v accelerated programming voltage v acc high voltage is applied 8.5 9.5 v low v cc f lock-out voltage note v lko 1.7 v note when v cc f is equal to or lower than v lko , the device ignores all write cycles. refer to dual operation flash memory 32m bits a series information (m14914e) . mobile specified ram parameter symbol test condition min. typ. max. unit high level output voltage v oh i oh = ? 0.5 ma v cc m 0.8 v low level output voltage v ol i ol = 1 ma v cc m 0.2 v operating supply current i cca /cem = v il , minimum cycle time, i i/o = 0 ma 35 ma standby supply standby mode 1 i sb1 /cem v cc m ? 0.2 v, mode v cc m ? 0.2 v 100 a current standby mode 2 i sb2 /cem v cc m ? 0.2 v, mode 0.2 v 10 !
data sheet m15414ej3v0ds 16 mc-242452 ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions flash memory input waveform (rise and fall time 5 ns) test points v ss 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load 1 ttl + 30 pf
data sheet m15414ej3v0ds 17 mc-242452 mobile specified ram input waveform (rise and fall time 5 ns) test points v cc m x 0.2 v v cc m x 0.8 v v cc m/2 v v cc m/2 v v cc m v ss 5 ns output waveform test points v cc m/2 v v cc m/2 v output load ac characteristics directed with the note should be measured with the output load shown in figure. c l : 50 pf 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , t ow ) i/o (output) 50 ? z o = 50 ? c l v cc m/2 v
data sheet m15414ej3v0ds 18 mc-242452 /cef, /cem timing parameter symbol test condition min. typ. max. unit note /cef, /cem recover time t ccr 0ns read cycle (flash memory) parameter symbol test condition min. typ. max. unit note read cycle time t rc 90 ns v cc f 2.7 v 85 address access time t acc /cef = /oe = v il 90 ns v cc f 2.7 v 85 /cef access time t cef /oe = v il 90 ns v cc f 2.7 v 85 /oe access time t oe /cef = v il 40 ns output disable time t df /oe = v il or /cef = v il 30 ns output hold time t oh 0ns /reset pulse width t rp 500 ns /reset hold time before read t rh 50 ns /reset low to read mode t ready 20 s /cef low to ciof low, high t elfl /t elfh 5ns ciof low output disable time t flqz 30 ns ciof high access time t fhqv 90 ns v cc f 2.7 v 85 remark t df is the time from inactivation of /cef or /oe to hi-z state output.
data sheet m15414ej3v0ds 19 mc-242452 write cycle (program / erase) (flash memory) parameter symbol min. typ. max. unit note write cycle time t wc 90 ns v cc f 2.7 v 85 address setup time (/we to address) t as 0ns address setup time (/cef to address) t as 0ns address hold time (/we to address) t ah 45 ns address hold time (/cef to address) t ah 45 ns input data setup time t ds 35 ns input data hold time t dh 0ns /oe hold time read t oeh 0ns toggle bit, data polling 10 read recovery time before write (/oe to /cef) t ghel 0ns read recovery time before write (/oe to /we) t ghwl 0ns /we setup time (/cef to /we) t ws 0ns /cef setup time (/we to /cef) t cs 0ns /we hold time (/cef to /we) t wh 0ns /cef hold time (/we to /cef) t ch 0ns write pulse width t wp 35 ns /cef pulse width t cp 35 ns write pulse width high t wph 30 ns /cef pulse width high t cph 30 ns byte programming operation time t bpg 9 200 s word programming operation time t wpg 11 200 s sector erase operation time t ser 0.7 5 s 1 v cc f setup time t vcs 50 s ry (/by) recovery time t rb 0ns /reset pulse width t rp 500 ns /reset high-voltage (v id ) hold time from high of ry(/by) t rrb 20 s when sector group is temporarily unprotect /reset hold time t rh 50 ns from completion of automatic t eoe 90 ns program / erase to data output time v cc f 2.7 v 85 ry (/by) delay time from valid program or erase operation t busy 90 ns address setup time to /oe low in toggle bit t aso 15 ns address hold time to /cef or /oe high in toggle bit t aht 0ns /cef pulse width high for toggle bit t ceph 20 ns /oe pulse width high for toggle bit t oeph 20 ns voltage transition time t vlht 4 s2 rise time to v id (/reset) t vidr 500 ns 3 rise time to v acc (/wp(acc)) t vaccr 500 ns 2 erase timeout time t tow 50 s4 erase suspend transition time t spd 20 s4 notes 1. the preprogramming time prior to the erase operation is not included. 2. sector group protection and accelerated mode only 3. sector group protection only. 4. table only.
data sheet m15414ej3v0ds 20 mc-242452 write operation (program / erase) performance (flash memory) parameter description min. typ. max. unit sector erase time excludes programming time prior to erasure 0.7 5 s chip erase time excludes programming time prior to erasure 50 s byte programming time excludes system-level overhead 9 200 s word programming time excludes system-level overhead 11 200 s chip programming time excludes system-level overhead byte mode 40 s word mode 25 accelerated programming time excludes system-level overhead 7 150 s program / erase cycle 100,000 cycle
data sheet m15414ej3v0ds 21 mc-242452 read cycle (mobile specified ram) parameter symbol mc-242452-b90 mc-242452-b95 mc-242452-b10 unit note min. max. min. max. min. max. read cycle time t rc 80 10,000 90 10,000 110 10,000 ns 1 identical address read cycle time t rc1 80 10,000 90 10,000 110 10,000 ns 2 address skew time t skew 10 15 20 ns 3 /cem pulse width t cp 10 10 10 ns address access time t aa 80 90 100 ns 4 /cem access time t acs 80 90 100 ns /oe to output valid t oe 35 40 50 ns 5 /lb, /ub to output valid t ba 35 40 50 ns output hold from address change t oh 10 10 10 ns /cem to output in low impedance t clz 10 10 10 ns /oe to output in low impedance t olz 555ns /lb, /ub to output in low impedance t blz 555ns /cem to output in high impedance t chz 25 25 25 ns /oe to output in high impedance t ohz 25 25 25 ns /lb, /ub to output in high impedance t bhz 25 25 25 ns notes 1. one read cycle (t rc ) must satisfy the minimum value (t rc(min.) ) and maximum value (t rc(max.) = 10 s). t rc indicates the time from the /cem low level input point or address determination point, whichever is later, to the /cem high level input point or the next address change start point, whichever is earlier. as a result, there are the following four conditions for t rc . 1) time from address determination point to /cem high level input point (address access) 2) time from address determination point to next address change start point (address access) 3) time from /cem low level input point to next address change start point (/cem access) 4) time from /cem low level input point to /cem high level input point (/cem access) 2. the identical address read cycle time (t rc1 ) is the cycle time of one read operation when performing continuous read operations toggling /oe , /lb, and /ub with the address fixed and /cem low level. perform settings so that the sum (t rc ) of the identical address read cycle times (t rc1 ) is 10 s or less. 3. t skew indicates the following three types of time depending on the condition. 1) when switching /cem from high level to low level, t skew is the time from the /cem low level input point until the next address is determined. 2) when switching /cem from low level to high level, t skew is the time from the address change start point to the /cem high level input point. 3) when /cem is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /cem is active, t skew is not subject to limitations when /cem is switched from high level to low level following address determination, or when the address is changed after /cem is switched from low level to high level. 4. regarding t aa and t acs , only t aa is satisfied during address access (refer to 1) and 2) of note 1 ), and only t acs is satisfied during /cem access (refer to 3) of note 1 ). 5. regarding t ba and t oe , only t ba is satisfied if /oe becomes active later than /ub and /lb, and only t oe is satisfied if /ub and /lb become active before /oe.
data sheet m15414ej3v0ds 22 mc-242452 write cycle (mobile specified ram) parameter symbol mc-242452-b90 mc-242452-b95 mc-242452-b10 unit note min. max. min. max. min. max. write cycle time t wc 80 10,000 90 10,000 110 10,000 ns 1 identical address write cycle time t wc1 80 10,000 90 10,000 110 10,000 ns 2 address skew time t skew 10 15 20 ns 3 /cem to end of write t cw 40 50 60 ns 4 /lb, /ub to end of write t bw 30 35 40 ns address valid to end of write t aw 35 45 55 ns write pulse width t wp 30 35 40 ns write recovery time t wr 20 20 20 ns 5 /cem pulse width t cp 10 10 10 ns address setup time t as 000ns byte write hold time t bwh 20 20 20 ns data valid to end of write t dw 20 25 30 ns data hold time t dh 000ns /oe to output in low impedance t olz 555ns /we to output in high impedance t whz 25 25 25 ns /oe to output in high impedance t ohz 25 25 25 ns output active from end of write t ow 555ns notes 1. one write cycle (t wc ) must satisfy the minimum value (t wc(min.) ) and the maximum value (t wc(max.) = 10 s). t wc indicates the time from the /cem low level input point or address determination point, whichever is after, to the /cem high level input point or the next address change start point, whichever is earlier. as a result, there are the following four conditions for t wc . 1) time from address determination point to /cem high level input point 2) time from address determination point to next address change start point 3) time from /cem low level input point to next address change start point 4) time from /cem low level input point to /cem high level input point 2. the identical address read cycle time (t wc1 ) is the cycle time of one write cycle when performing continuous write operations with the address fixed and /cem low level, changing /lb and /ub at the same time, and toggling /we, as well as when performing a continuous write toggling /lb and /ub. make settings so that the sum (t wc ) of the identical address write cycle times (t wc1 ) is 10 s or less. 3. t skew indicates the following three types of time depending on the condition. 1) when switching /cem from high level to low level, t skew is the time from the /cem low level input point until the next address is determined. 2) when switching /cem from low level to high level, t skew is the time from the address change start point to the /cem high level input point. 3) when /cem is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /cem is active, t skew is not subject to limitations when /cem is switched from high level to low level following address determination, or when the address is changed after /cem is switched from low level to high level.
data sheet m15414ej3v0ds 23 mc-242452 4. definition of write start and write end /cem /we /lb, /ub status write start pattern 1 h to l l l if /we, /lb, /ub are low level, time when /cem changes from high level to low level write start pattern 2 l h to l l if /cem, /lb, /ub are low level, time when /we changes from high level to low level write start pattern 3 l l h to l if /cem, /we are low level, time when /lb or /ub changes from high level to low level write end pattern 1 l l to h l if /cem, /we, /lb, /ub are low level, time when /we changes from low level to high level write end pattern 2 l l l to h when /cem, /we, /lb, /ub are low level, time when /lb or /ub changes from low level to high level 5. definition of write end recovery time (t wr ) 1) time from write end to address change start point, or from write end to /cem high level input point 2) when /cem, /lb, /ub are low level and continuously written to the identical address, time from /we high level input point to /we low level input point 3) when /cem, /we are low level and continuously written to the identical address, time from /lb or /ub high level input point, whichever is later, to /lb or /ub low level input point, whichever is earlier. 4) when /cem is low level and continuously written to the identical address, time from write end to point at which /we , /lb, or /ub starts to change from high level to low level, whichever is earliest. read write cycle (mobile specified ram) parameter symbol mc-242452-b90 mc-242452-b95 mc-242452-b10 unit note min. max. min. max. min. max. read write cycle time t rwc 10,000 10,000 10,000 ns 1, 2 byte write setup time t bws 20 20 20 ns byte read setup time t brs 20 20 20 ns notes 1. make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cem low level, or when a write is performed using /lb following a read using /ub. 2. make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a read is performed at the identical address using /ub following a write using /lb with /cem low level, or when a read is performed using /lb following a write using /ub.
data sheet m15414ej3v0ds 24 mc-242452 figure 1. alternating mobile specified ram to flash memory timing chart /cef (input) /cem (input) t ccr t ccr figure 2. read cycle timing chart 1 (flash memory) address (input) /cef (input) /oe (input) /we (input) hi-z data out t oeh t oh t oe t cef t rc t acc t df hi-z i/o (output) figure 3. read cycle timing chart 2 (flash memory) address (input) /reset (input) t acc hi-z data out hi-z i/o (output) t rc /cef (input) t rh t rp t oh t cef t ready
data sheet m15414ej3v0ds 25 mc-242452 figure 4. sector group protection timing chart (flash memory) sgax sgax address (input) a0 (input) a1 (input) a6 (input) /cef (input) /reset (input) v cc f /oe (input) /we (input) i/o (input/output) t wc t vcs t vlht t vidr t wc t oe timeout t wp sgay 60h 60h 40h 01h note 60h v id v ih note the sector group protection verification result is output. 01h : the sector group is protected. 00h : the sector group is not protected. figure 5. temporary sector group unprotect timing chart (flash memory) /reset (input) v cc f /we (input) /cef (input) ry (/by) (output) v id v ih t vlht t vcs t vidr t rrb t vlht t vlht (program or erase command sequence) period during which protection is canceled
data sheet m15414ej3v0ds 26 mc-242452 figure 6. accelerated mode timing chart (flash memory) /wp (acc) (input) v cc f /we (input) /cef (input) ry (/by) (output) v acc v ih t vlht t vcs t vaccr t vlht t vlht (program or erase command sequence) accelerated mode period figure 7. dual operation timing chart (flash memory) address (input) /cef (input) /oe (input) /we (input) i/o (input / output) t as ba1 t rc t ah input output output ba2 ba1 ba2 ba1 ba2 t wc t rc t wc t rc t wc t acc t cef t ceph t aht t as t oe t df t wp t ghwl t ds t dh t df t oeh input output status
data sheet m15414ej3v0ds 27 mc-242452 figure 8. write cycle timing chart (/we controlled) (flash memory) address (input) /cef (input) /oe (input) /we (input) i/o (input / output) t ds t dh t ghwl t cs t wph t bpg or t wpg t wc t as t ah t ch pd /i/o7 d out t oh t oe t cef t rc 555h pa pa a0h (3rd and 4th write cycle) d out t wp (data polling) remarks 1. this timing chart shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. this timing chart shows the word mode ? s case. in the byte mode, address to be input are different from the word mode. see command sequence (flash memory) . 3. pa : program address pd : program data /i/o7 : the output of the complement of the data written to the device. d out : the output of the data written to the device. figure 9. write cycle timing chart (/cef controlled) (flash memory) address (input) /cef (input) /oe (input) /we (input) i/o (input / output) t ds t ghel t ws t bpg or t wpg t wc t as t ah pd /i/o7 d out t oh t oe t cef t rc 555h pa pa a0h (3rd and 4th write cycle) d out t wh t dh t cp t cph (data polling) remarks 1. this timing chart shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. this timing chart shows the word mode ? s case. in the byte mode, address to be input are different from the word mode. see command sequence (flash memory) . 3. pa : program address pd : program data /i/o7 : the output of the complement of the data written to the device. d out : the output of the data written to the device.
data sheet m15414ej3v0ds 28 mc-242452 figure 10. sector / chip erase timing chart (flash memory) address (input) /cef (input) /oe (input) /we (input) i/o (input) v cc f t ds t dh t ch t cs t wph 555h t wc t as t ah t wp 55h aah 80h aah 55h (10h for chip erase) 30h 2aah 555h 555h 2aah fsa note t ghwl t vcs note fsa is the sector address to be erased. in the case of chip erase, input 555h (word mode), aaah (byte mode). remark this timing chart shows the word mode ? s case. in the byte mode, address to be input are different from the word mode. see command sequence (flash memory) . figure 11. data polling timing chart (flash memory) /cef (input) t oeh t oe t bpg, t wpg, t ser t cef hi-z t ch /oe (input) /we (input) i/o7 (output) ry (/by) (output) t eoe /i/o7 valid data hi-z i/o0 - i/o6 (output) t df t busy d out note status data note i/o7 = d out : true value of program data (indicates completion of automatic program / erase)
data sheet m15414ej3v0ds 29 mc-242452 figure 12. toggle bit timing chart (flash memory) /oe (input) /we (input) /cef (input) address (input) i/o6, i/o2 (input / output) t as t aso t aht t aht t ceph t oeph t oeh t busy t dh t oeh t cef t oe input data toggle toggle valid data out stop toggling note toggle ry (/by) (output) note i/o6 stops the toggle (indicates automatic program / erase completion). figure 13. i/o2 vs. i/o6 timing chart (flash memory) /we (input) input of automatic erase command erase suspended erasure resumed erase suspended input of program command erase suspended input of program command erase suspended read erase suspended read erasure erasure completion of erasure toggle i/o6 (output) i/o2 (output) i/o2 and i/o6 (/cef or /oe is used for toggle) figure 14. ry (/by) (ready / busy) timing chart (flash memory) /cef (input) /we (input) ry (/by) (output) t busy automatic program or erase rising edge of the last write pulse figure 15. /reset and ry (/by) timing chart (flash memory) /we (input) /reset (input) ry (/by) (output) t rp t ready t rb
data sheet m15414ej3v0ds 30 mc-242452 figure 16. write ciof timing chart (flash memory) /cef, /we (input) ciof (input) input determined t ah t as falling edge of last write pulse figure 17. byte mode switching timing chart (flash memory) /cef (input) ciof (input) i/o0 - i/o14 (output) hi-z i/o15 (output), a ? 1 (input) t elfl t acc t flqz hi-z hi-z data output i/o0-i/o14 data output i/o15 data output i/o0-i/o7 address input a ? 1 figure 18. word mode switching timing chart (flash memory) data output i/o15 /cef (input) ciof (input) i/o0 - i/o14 (output) i/o15 (output), a ? 1 (input) t elfh t fhqv t cef hi-z hi-z hi-z data output i/o0-i/o14 data output i/o0-i/o7 address input a ? 1
data sheet m15414ej3v0ds 31 mc-242452 figure 19. read cycle timing chart 1 (mobile specified ram) t chz t oh t clz t acs hi-z t blz t ba t bhz t oe t skew t skew t cp t cp t rc t olz t ohz t chz t clz t aa hi-z t blz t ba t bhz t oe t skew t cp t cp t rc t olz t ohz t skew address (input) /cem (input) /oe (input) i/o (output) /lb, /ub (input) address (input) /cem (input) /oe (input) i/o (output) /lb, /ub (input) data out data out caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high.
data sheet m15414ej3v0ds 32 mc-242452 t aa t rc t skew t skew t rc t skew hi-z t aa t oe t olz t blz t oh t cp t rc t chz t acs t clz t bhz t ba t blz t skew t cp t rc t chz t acs t clz t bhz t ba t blz t bhz t chz t oh t aa t ohz t rc t clz t ba t oh address (input) /cem (input) /oe (input) i/o (output) /lb, /ub (input) data out data out data out data out data out caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high. figure 20. read cycle timing chart 2 (mobile specified ram)
data sheet m15414ej3v0ds 33 mc-242452 t aa t rc t skew t clz t rc t skew t rc t skew t rc t skew t rc t skew hi-z hi-z t blz t blz t olz t oe t ba t ba t oh t bhz t bhz t ohz t oh t oh t bhz t ohz t oh t bhz t ohz t aa t blz t olz t oe t ba t blz t olz t oe t ba t aa address (input) /cem (input) /oe (input) i/o0 - 7 (output) /lb (input) i/o8 - 15 (output) /ub (input) data out data out data out data out caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value f or the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high. figure 21. read cycle timing chart 3 (mobile specified ram)
data sheet m15414ej3v0ds 34 mc-242452 figure 22. read cycle timing chart 4 (mobile specified ram) t skew t skew hi-z hi-z t rc1 t ba t ba t rc1 t rc t aa t oe t oe t olz t blz t olz t blz t ohz t bhz t ohz t bhz address (input) /cem (input) /oe (input) i/o (output) /lb, /ub (input) data out data out note note caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. note to perform a continuous read toggling /oe, /ub, and /lb with /cem low level at an identical address, make settings so that the sum (t rc ) of the identical address read cycle times (t rc1 ) is 10 s or less. remark in read cycle, /we should be fixed to high.
data sheet m15414ej3v0ds 35 mc-242452 figure 23. write cycle timing chart 1 (mobile specified ram) t bw t dw t dh hi-z t wp t wr t skew t cp hi-z t wc t aw t skew t dw t dh t as t wp t wr t as t bw t wc t aw t bw t dw t dh hi-z t wp t wr t skew t cp hi-z t wc t skew t dw t dh t wp t wr t bw t wc t cw t cw t skew address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 36 mc-242452 figure 24. write cycle timing chart 2 (mobile specified ram) t cw t aw t as t wp t skew t wc t skew t aw t dw t dh t wr t ow t aw t skew t cp t whz hi-z hi-z hi-z hi-z hi-z t ohz t olz t wc t wc t wp t wp t wr t wr t dw t dh t dw t dh t skew t dw t dh t skew t skew hi-z hi-z hi-z t wc1 t as t wp t wp t wr t dw t dh t wc1 t bw t skew t wc t wr address (input) /cem (input) /we (input) i/o (intput / output) /oe (input) address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in indefinite data out data in data in data in data in note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cem low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remarks 1. write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub. 2. when /we is at low, the i/o pins are always high impedance. when /we is at high, read operation is executed. therefore /oe should be at high to make the i/o pins high impedance.
data sheet m15414ej3v0ds 37 mc-242452 figure 25. write cycle timing chart 3 (/cem controlled) (mobile specified ram) t as t cw t wr t wc t dw t dh hi-z hi-z hi-z t wc t dw t dh t cw t wr t as t as t cw t wr t wc t dw t dh hi-z hi-z hi-z t wc t dw t dh t cw t wr t as address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 38 mc-242452 figure 26. write cycle timing chart 4 (/lb, /ub controlled 1) (mobile specified ram) t bw t dw t dh hi-z t wp t wr t skew hi-z t wc t aw t skew t dw t dh t as t wc t aw t bw t as t wr t bw t dw t dh hi-z t wp t wr t skew hi-z t wc t cw t skew t dw t dh t as t wc t bw t as t wr t aw address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 39 mc-242452 figure 27. write cycle timing chart 5 (/lb, /ub controlled 2) (mobile specified ram) t dw t dh t skew t skew hi-z hi-z hi-z t wc1 t as t bw t bw t wr t dw t dh t wc1 t wr t wc t wp data in data in address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cem low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 40 mc-242452 figure 28. write cycle timing chart 6 (/lb, /ub independent controlled 1) (mobile specified ram) t wp t as t cw t wr t wc1 t bw hi-z hi-z t bw t wc1 t dw t dh t wr hi-z hi-z t dw t dh t wc address (input) /cem (input) /we (input) i/o0 - 7 (intput) /lb (input) i/o8 - 15 (intput) /ub (input) data in data in note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cem low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 41 mc-242452 figure 29. write cycle timing chart 7 (/lb, /ub independent controlled 2) (mobile specified ram) t wp t as t cw t wc t bw hi-z hi-z t bw t dw t dh hi-z hi-z t dw t dh t wr t wr t as t bwh t cw t wp address (input) /cem (input) /we (input) i/o0 - 7 (intput) /lb (input) i/o8 - 15 (intput) /ub (input) data in data in cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 42 mc-242452 figure 30. read write cycle timing chart 1 (/lb, /ub independent controlled 1) (mobile specified ram) t wp t bws t rc1 hi-z hi-z t bw t wc1 t wr hi-z hi-z t dw t dh t rwc t clz t blz t bhz t acs t aa address (input) /cem (input) /we (input) i/o0 - 7 (output) /lb (input) i/o8 - 15 (intput) /ub (input) data out data in note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cem low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 43 mc-242452 figure 31. read write cycle timing chart 2 (/lb, /ub independent controlled 2) (mobile specified ram) t wp t rc1 hi-z hi-z t bw t wc1 t wr hi-z hi-z t dw t dh t rwc t blz t bhz t brs t ba t cw t as address (input) /cem (input) /we (input) i/o0 - 7 (input) /lb (input) i/o8 - 15 (output) /ub (input) data in data out note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cem low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 44 mc-242452 figure 32. read write cycle timing chart 3 (/lb, /ub independent controlled 3) (mobile specified ram) address (input) /cem (input) /we (input) i/o0 - 7 (input) /lb (input) i/o8 - 15 (output) /ub (input) t bw t rc1 hi-z hi-z t wp t wc1 t wr hi-z hi-z t dw t dh t rwc t blz t bhz t ba t cw t as data in data out note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cem low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
data sheet m15414ej3v0ds 45 mc-242452 figure 33. standby mode 2 entry and recovery timing chart (mobile specified ram) address (input) /cem (input) mode (input) t cm t rc t cp standby mode 2 wait time 200 s read operation 8 times normal operation parameter symbol min. max. unit note /cem high to mode low t cm 0ns cautions 1. make mode and /cem high level during the wait time interval. 2. make mode high level during the wait time and eight read operations. 3. the read operation must satisfy the specs (read cycle (mobile specified ram)). 4. the address is don ? t care (v ih or v il ) during read operation. 5. read operation must be executed with toggled the /cem pin. 6. to prevent bus contention, it is recommended to set /oe to high level. however, do not input data to the i/o pins if /oe is low level during a read operation. flow charts (flash memory) refer to dual operation flash memory 32m bits a series information (m14914e). !
data sheet m15414ej3v0ds 46 mc-242452 cfi code list (1/2) address a6 to a0 data i/o15 to i/o0 description 10h 0051h "qry" (ascii code) 11h 0052h 12h 0059h 13h 0002h main command set 14h 0000h 2 : amd/fj standard type 15h 0040h start address of primary table 16h 0000h 17h 0000h auxiliary command set 18h 0000h 00h : not supported 19h 0000h start address of auxiliary algorithm table 1ah 0000h 1bh 0027h minimum v cc f voltage (program / erase) i/o7 to i/o4 : 1 v/bit i/o3 to i/o0 : 100 mv/bit 1ch 0036h maximum v cc f voltage (program / erase) i/o7 to i/o4 : 1 v/bit i/o3 to i/o0 : 100 mv/bit 1dh 0000h minimum v pp voltage 1eh 0000h maximum v pp voltage 1fh 0004h typical word program time (2 n s) 20h 0000h typical buffer program time (2 n s) 21h 000ah typical sector erase time (2 n ms) 22h 0000h typical chip erase time (2 n ms) 23h 0005h maximum word program time (typical time 2 n ) 24h 0000h maximum buffer program time (typical time 2 n ) 25h 0004h maximum sector erasing time (typical time 2 n ) 26h 0000h maximum chip erasing time (typical time 2 n ) 27h 0016h capacity (2 n bytes) 28h 0002h i/o information 29h 0000h 2 : 8/ 16-bit organization 2ah 0000h maximum number of bytes when two banks are programmed (2 n ) 2bh 0000h 2ch 0002h type of erase block 2dh 0007h information about erase block 1 2eh 0000h bit0 to 15 : y = number of sectors 2fh 0020h bit16 to 31 : z = size 30h 0000h (z 256 bytes)
data sheet m15414ej3v0ds 47 mc-242452 (2/2) address a6 to a0 data i/o15 to i/o0 description 31h 003eh information about erase block 2 32h 0000h bit0 to 15 : y = number of sectors 33h 0000h bit16 to 31 : z = size 34h 0001h (z 256 bytes) 40h 0050h "pri" (ascii code) 41h 0052h 42h 0049h 43h 0031h main version (ascii code) 44h 0032h minor version (ascii code) 45h 0000h address during command input 00h : necessary 01h : unnecessary 46h 0002h temporary erase suspend function 00h : not supported 01h : read only 02h : read / program 47h 0001h sector group protection 00h : not supported 01h : supported 48h 0001h temporary sector group protection 00h : not supported 01h : supported 49h 0004h sector group protection algorithm 4ah 00xxh number of sectors of bank 2 00h : not supported 38h : mc-242452 4bh 0000h burst mode 00h : not supported 4ch 0000h page mode 00h : not supported 4dh 0085h minimum v acc voltage i/o7 to i/o4 : 1 v/bit i/o3 to i/o0 : 100 mv/bit 4eh 0095h maximum v acc voltage i/o7 to i/o4 : 1 v/bit i/o3 to i/o0 : 100 mv/bit 4fh 00xxh boot organization 02h : bottom boot 50h 0001h temporary program suspend function 00h : not supported 01h : supported
data sheet m15414ej3v0ds 48 mc-242452 package drawings 77-pin tape fbga (12x7) s x e ab m s wb w sa s y s y1 item millimeters d 12.0 0.1 7.0 0.1 e 0.2 b 0.45 0.05 x 0.08 y 0.1 y1 0.1 zd 0.7 ze 0.8 w a 1.1 0.1 a1 0.26 0.05 a2 0.84 p77f9-80-bt3 b ? index mark a 0.8 e a1 a2 s a b zd ze pnmlkjhgf edcba 8 7 6 5 4 3 2 1 d e
data sheet m15414ej3v0ds 49 mc-242452 s wb s wa 8 7 6 5 4 3 2 1 b a b c d e f g h j k l m a s y s y1 s ? s x bab m 71-pin tape fbga (11x7) item millimeters d 7.00 0.10 e 11.00 0.10 w 0.20 a 1.11 0.10 a2 0.84 a1 0.27 0.05 a a2 a1 e ze zd b 0.45 0.05 x 0.08 y 0.10 y1 0.20 0.80 e zd 0.70 ze 1.10 e d index mark p71f9-80-bs1 !
data sheet m15414ej3v0ds 50 mc-242452 recommended soldering conditions please consult with our sales offices for soldering conditions of the mc-242452. types of surface mount device mc-242452f9-bt3 : 77-pin tape fbga (12 7) mc-242452f9-bs1 : 71-pin tape fbga (11 7) !
data sheet m15414ej3v0ds 51 mc-242452 revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 3rd edition/ throughout throughout modification preliminary data sheet data sheet march 2002 addition 71-pin tape fbga (11 7) p.3 p.3 modification pin configurations 77-pin tape fbga (12 7): f8, g8: v ss ic, h7: v ss nc, l5: v cc m nc addition note 2 ? p.5, 6 deletion contents p.5 p.7 addition bus operations table remark 4 ? p.7 to 10 deletion 1. bus operations, explanation p.13 to 20 3. commands, p.21 to 23 4. hardware sequence flags, p.24 5. hardware data protection p.8 ? addition sector group address table p.10 p.14 modification command sequence remark 2: spa, sua addition remark 6 p.11 ? addition reference comment of information p.14 p.27 deletion electrical specifications capacitance p.15 p.28 modification dc characteristics (flash memory) note: reference comment of information p.45 p.58 addition reference comment of information ? p.59 to 63 deletion 8. flow chart
data sheet m15414ej3v0ds 52 mc-242452 [ memo ]
data sheet m15414ej3v0ds 53 mc-242452 [ memo ]
data sheet m15414ej3v0ds 54 mc-242452 [ memo ]
data sheet m15414ej3v0ds 55 mc-242452 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
mc-242452 related documents document name document number dual operation flash memory 32m bits a series information m14914e m8e 00. 4 the information in this document is current as of march, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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